Design of Fast Transient Low-Dropout Voltage Regulator with an Error Amplifier

This paper presents a Low dropout voltage regulator with an error amplifier; which eliminates the use of large capacitors in the output of the regulator. The use of error amplifier reduces the error voltage and improves the transient response of the LDO regulator. The proposed circuit was implemented with a power supply voltage of 1.8V in 0.18?m standard technology. The LDO circuit consumes a quiescent current of 12.2mA with a dropout voltage of 200mV. The proposed LDO architecture supports higher load transients and provides stability when used in analog circuits.