Implementation of High Speed FFT using Reliable Multiplier with AHL Circuit

Fast Fourier Transform (FFT) is used to convert a signal from Time domain to frequency domain. FFT and IFFT algorithm plays an important role in design of digital signal processing. An FFT is an algorithm that speeds up the calculation of a DFT.FFT is a DFT for speed. The entire purpose of an FFT is to speed up the calculations. This paper describes the design of Decimation in Time-Fast Fourier Transform (DIT-FFT). The proposed design is implemented with radix-2, based 4 point FFT. Whereas digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Here a reliable multiplier with adaptive hold logic is used. This approach reduces the multiplicative complexity which exists in conventional FFT implementation. For the number representation of FFT fixed point arithmetic has been used. The overall performance of the FFT is based on the throughput of the Multiplier. Here the multiplier with AHL is used to reduce the power consumption and to increase the speed of the FFT.The design is implemented using Verilog HDL language.