An Efficient VLSI Implementation of First Two Minimum Value Generator for Bit Serial LDPC Decoder

Low Density Parity Check code has excellent error correcting capability and parallel structure, A low-complexity generator is crucially important, Because the hardware complexity of generator utilizes a significant portion of the min sum Low ?Density Parity Check Decoder. To reduce hardware complexity an existing bit-serial generator that finds only one minimum value instead of two has been proposed; however they use minimum value generator to design a decoder, proposed low complexity bit-serial generator can find the exact first two minimum values, and thus can improve the Bit Error Rate performance. Moreover, the proposed generator does not suffer from any throughput loss since its latency is almost the same as that of the existing generator. The Proposed System designed using Verilog HDL and Simulated by Modelsim 6.4a and Synthesized by Xilinx tool. The proposed system implemented in Spartan 3E 3S250E PQ 208 FPGA.