IDDT-Based Fault Detection and Localization in 10-T Sub-Threshold SRAM Memory Array

In some of the portable, power crucial and not-timing crucial applications more than 90% of the chip area will be occupied by memories and are powered by batteries. As in few applications batteries cannot be recharged it is very essential to reduce the power consumed by memory in order to increase the battery life time. Such application demand low power memories. In recent years a lot of work has been done on designing sub-threshold memories those can successfully operate at low voltages. However, test methods to unveil physical defects in those new memory architectures have not been fully developed. Existing voltage based test methods fail to cover most of the weak opens and also there is no single test method which can unveil all defects in the memory cell. Moreover, the localization of faulty cell in a memory array is not possible. In this work, a dynamic current based delay testing technique which monitors the time at which the abnormal current appears due to fault is used to locate faults. Through simulations it is also found that the minimum detectable resistance is lesser in the proposed technique and thus defect detection in process technology.