FPGA IMPLEMENTATION OF A COMPACT AES ALGORITHM WITH S-BOX OPTIMIZATION

This paper proposes a compact AES algorithm to achieve less slice consumption of FPGA. Proposed design is based on iterative round looping architecture. S-box is implemented using composite field arithmetic which requires less area than lookup table.We used same S-box for key expansion block. This design supports 128-bits key size. It uses 8-bit data path to decrease the parallelism of operations and therefore reduces the hardware utilization.Synthesis of our complete design is done using Xilinx ISE 14.5 and implemented on Spartan 3 FPGA using VHDL language. GUI is developed in visual basics 6.0. This GUI is used to send a plain text and key for encryption. Decrypted data is also displayed on the same. The results from the Place and Route report indicate that area occupied by this architecture is 680 slices. This design is very well suited for small embedded applications.