PIPELINED FPGA PROTOTYPING OF DIGITAL VIDEO STABILIZATION SYSTEM FOR REALTIME IMPLEMENTATIONS

Video Stabilization has been one of the more commonly used video processing operations. Despite the fact that many advances have been made in the field, off late researches have been dedicated to applications that demand compact solutions and immediate real time outputs. This work deals with specific implementation perspectives of real-time Stabilization required for video capturing systems mounted on offroad vehicles, UAVs. The work implemented a fully pipelined Digital Video Stabilization system employing USURF feature detection which has proven to be less computationally demanding as compared to the prevalent mechanisms and hence offers a viable solution for compact real-time applications. The implementation has been done on a Xilinx Zynq XC7030 board with the resource utilization results asserting the compactness and real time performance of our design architecture of the algorithm. We have achieved significantly better PSNR gains of the order of 46% and MSE reduction of the order of 40% than the existing compared works. The implementation has been done using Verilog and testing has been done using 3 standard datasets StableNet Dataset, StabNet Dataset and the MATLAB Computer Vision Toolbox Dataset.