RECENT TREND BASED WALLACE TREE MULTIPLIER AIMING TO LOW LEAKAGE POWER

A new domino circuit is proposed with low leakage and high noise immunity which decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper for wide fan-in gates to implement fast and robust circuits. The technique utilized is based on comparison of mirrored current of the pull-up network with its worst case leakage current. Thus, the power consumption and delay are reduced. A 4*4 Wallace tree multiplier is designed based on CCD (Current Comparison Domino) which uses low leakage high speed full adders. These full adders uses current comparison based domino logic to achieve low leakage and high speed. The proposed 4*4 Wallace tree multiplier using current comparison based domino logic full adders was simulated using 180nm CMOS technology which shows a relative power reduction when compared to the 4*4 Wallace tree multiplier using standard full adders.