PERFORMANCE EVALUATION IN TERMS OF LATENCY AND POWER OF SOURCE ROUTING ALGORITHM USING MESH NOC ARCHITECTURE FOR BURSTY TRAFFIC

With the development of integration technology, system-on-chip (SoC), composed of heterogeneous cores on a single chip, has entered the billion transistors era. Development of a complete system on a single chip became due to advancement in chip capacity which is the number of transistors that can be fabricated on a chip. But in SoC there are certain limitations of buses and interconnections. The most suitable candidate for implementing interconnections in core based system on chip is being considered as NoC. Cores are connected to each other through a network of routers and they communicate among themselves through a packet-switched communication in NoC. Significant reuse of resources and highly scalable and flexible communication infrastructure for SoC design is provided by NoC. This paper proposes a network on chip architecture with mesh topology and source routing algorithm. In this paper we review the performance of source routing algorithm of mesh NoC architecture for bursty traffic. The performance of propose architecture is evaluate based on metrics of latency and power per channel under bursty traffic.