DESIGN AND IMPLEMENTATION OF SERIAL DIVIDER USING 180NM PROCESS TECHNOLOGY

This paper presents an efficient 4-bit unsigned binary serial divider and its implementation using 180nm CMOS process technology. The layout design of the serial divider circuit is efficiently optimized in terms of area. The serial divider circuit provides a good compromise between area and performance in divider design. The serial divider is designed based on repeated one’s complement binary subtraction algorithm. The implementation consists of several combinational and sequential components such as 4-bit ripple carry adder, 2:1 multiplexers, D flip-flops and 4-bit synchronous up counter. The circuit analysis is carried out in terms of performance parameters such as transistor count, propagation delay and power consumption. According to the estimations done, the transistor count, propagation delay and power consumption of the serial divider without parasitics was found to be 568, 5.13ns and 196.2?W respectively.The presence of parasitics due to metal layers in the layout design increase propagation delay to 86.42ns and power consumption to 206?W.