2E15 -1 TERA BITS PER SECOND (TBPS) PRBS HDL ASIC IP DESIGN

The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of Tbps Data Rate using 2e15-1 Tapped PRBS Pattern Sequence. The PRBS is Designed by using LFSR Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points as per CCITT ITU Standards. RTL Design Architecture Implemented by using VHDL &/ Verilog HDL, Programming & Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O.