AN OPTIMIZED AES CRYPTOGRAPHY FOR NETWORK SECURITY IN VLSI DESIGN

As the data to be made safer, network protection is one of the most critical principles of data security. There are a variety of algorithms, such as AES, that can be used to protect data (Advanced Encryption Standard). The reliability of data encryption and authentication can be improved by using structured and proven-secure block cyphers such as the advanced encryption standard (AES). However, these protection functions use a significant amount of computing capacity and resources. Our hardware optimization techniques for AES for high-speed ultralow-power ultralow-energy IoT applications with multiple layers of protection are presented in this article. Via various key sizes, power and energy optimization for both datapath and key extension, our architecture supports several protection levels. The process of designing and utilising a cryptosystem or cypher to prohibit anyone but the expected receiver from accessing or using the knowledge or application encrypted is known as cryptography. The calculated power findings indicate that our implementation will achieve an energy per bit of less than 1 pJ/b at 10 MHz at 0.6 V with a throughput of 28 Mb/s in ST FDSOI 28-nm technology, which is comparable to the lightweight standardised algorithm PRESENT. In terms of security, a correlation power analysis attack utilising less than 20 000 traces cannot expose our proposed datapath's 32-b key out of 128-b key