FPGA IMPLEMENTATION OF 8-BIT PARALLEL CYCLIC REDUNDANCY CODE

This paper presents a different ways to solve the parallel CRC circuit. Certain drawbacks were observed in the without FPGA board. Some techniques used Linear feedback shift registers (LFSR) to do serial implementation. This origin resulted in a circuit that was inefficient in terms of time utilization because of parallel communication. We have worked on the related problems and have proposed an efficient mechanism. We have improve the VHDL code using VHDL structural modeling. The work was also compared with existing models of parallel implementation of eight bit CRC circuit. The code is written for eight bit parallel CRC and FPGA implementation of the code was done. Comparing with existing work, the model is more efficient in terms of hardware utilization. As the hardware utilization has been done in an efficient way, the overall efficiency of the parallel CRC is found to develop.