EFFECTIVE HARDWARE ENACTMENT OF LED BLOCK CIPHER

Resource constrained devices such as RFID and sensor nodes contain sensitive and confidential information. Such devices are used in many applications leading to an ever increasing need to provide high speed security. In order to satisfy these constraints in the small embedded applications which have limited resources, lightweight symmetric LED block cipher plays a major role in the bulk data encryption. In this paper implementation of a hardware efficient symmetric LED (Light Encryption Device) block cipher design that increasing speed using high speed parallel sub-pipelined architecture is proposed. This approach is done for block size of 128-bits and key size of 128-bits. The trade of between the low resource requirement and cryptographic strength is balanced here. It is tested by encrypting and decrypting a single 128 bit block. The algorithm was designed using VHDL. To verify the digital design at the software platform modalism simulator Altera 6.5e is used and synthesized using the Xilinx synthesizer and targeted in low cost FPGA device Spartan 6.