Design of Low Power, Area Efficient and High Stability Multiple Frequency Output Phase Locked Loop for Multiphase Clocking Circuits

A phase locked loop (PLL) is a key element of many communication and instrumentation domain. It is a key element in clock generation. The proposed paper presents the design of low power, area efficient and high stability multiple frequency output of PLL using high performance and low power VCO for fast frequency locking. The PLL is designed in Microwind EDA in design environment using 32nm CMOS technology with operating frequency of 1 GHz and lock time of 100ns. We are using high performance VCO with wide frequency range of 1.59 GHz to 3.52 GHz. The PLL consumes total power of 0.118 mw with the technology supply voltage of 1 V. The PLL is designed with multiple output frequency locking as 3.67 GHz, 1.87 GHz, 0.86 GHz, and 0.42 GHz with an efficient area as 57.5?m2.