A NOVEL TOPOLOGY FOR MULTILEVEL INVERTER USING FPGA
期刊名字: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.4, No. 3)Publication Date: 2015-03-30
论文作者 : Sofia A; BinduPrakas; Remya R Krishnan; Reeja J; Aswathi S Thilak;
起始页码 : 445-449
关键字 : Multilevel inverter; power electronics; Phase Disposition SPWM; Reverse voltage topology; FPGA.;
论文摘要
Multi level inverter has been dominating the engineering field over the last few decades. However the output waveform of the present inverter possesses undesirably large harmonic content. The main purpose of this paper is to implement a multilevel inverter with output waveform having less total harmonic distortion. The novel topology introducedhere is known as the reverse voltage topology. The notable advantage of this topology is the minimum requirement of components and carriers signals. The end result is a substantial reduction in the overall cost and complexity. Other advantages include lower Total Harmonic Distortion (THD), less stress on the power switches and higher efficiency. FPGA plays the role of the controller. Finally, a prototype of the nine-level proposed topology is built and tested to show the performance of the inverter by experimental results. The proposed topology and its control method are explained and detailed simulation has been carried out in MATLAB/ simulink.
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更新日期: 2015-04-07 22:25:07