Design of reversible binary logarithmic multiplier and divider using optimal garbage

Energy efficient test-able binary logarithmic multiplier and divider architecture using reversible logic has been reported in this paper. The focus of this paper is to avoid multiplication and division stages to reduce large layout area and make the circuit efficiently test-able. Here all the computations have been performed in radix-2 basis. Moreover to avoid the usage of large number of constant inputs, an efficient technique has been adopted. Though the procedure demands errors in the result, efforts have been made to achieve higher accuracy.