An optimized design of serial logic comparator

Comparator is a combinational circuit which is used to compare the values by taking two numbers as input and determines whether one number is greater than, less than or equal to the other number. Comparators have many applications in mainstream electronics and modern digital VLSI design, such as – Threshold Detector, Zero crossing Detector, Relaxation Oscillator, Schmitt Trigger and digital signal processors. This paper presents an efficient serial comparator design by block optimization techniques. The proposed 8-bit binary serial comparator is designed using a parallel to serial converter circuit as first stage that converts parallel data into serial rotated data. The second stage involves implementing a switching circuit in order to place data in two-comparison shift register. Only Most Significant Bit values of the two registers are compared through one-bit comparator cell as the third stage. The design and simulation of the proposed miniaturized global circuit of the serial comparator has been implemented by using DSCH 3.5 and Microwind 2.0 software showing a good quality performance. Moreo-ver, the paper describes the simulation of layout and parametric analysis for the proposed 8-bit comparator design. It is noted that the area cost, the number of cycles and power consumption values are less in the proposed technique compared to the existing approaches.