Capacitance Based Low Power ALU Design and Implementation on 28nm FPGA
Journal: International Journal of Scientific Engineering and Technology (IJSET) (Vol.2, No. 6)Publication Date: 2013-06-01
Authors : Bishwajeet Pandey Jyotsana Yadav Deepa Singh Viswam Parthiban;
Page : 465-468
Keywords : LVCMOS; IO standard; Low Power; Energy Efficient Design; Capacitance Scaling;
Abstract
In this work, capacitance and technology scaling is used for further reduction in IOs power. On 40nm technology and 10 GHz operating frequency, there is 4.59%, 9.38%, 13.97% and 18.76% reduction in IOs power when capacitance change from 5pF to 4pF, 3pF, 2pF and 1pF respectively. On 28nm technology and 10 GHz operating frequency, there is 5.54%, 11.32%, 16.86%, and 20.72% reduction in IOs power when capacitance changes from 5pF to 4pF, 3pF, 2pF and 1pF respectively. There is 17.16% and 17.99% reduction in power on 5pF and 4pF capacitance respectively on 10 GHz. There is 18.94%, 19.95% and 19.16% reduction in power on 3pF, 2pF and 1pF capacitance respectively on 10GHz. Target Device is Virtex-6 for 40nm and Artix-7 for 28nm.
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Last modified: 2013-06-08 20:41:26