Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

The conventional silicon channel metal oxide semiconductor field effect transistor (MOSFET) has fundamental limits that are reached due to scalability, resulting in short-channel effects (SCE) and other issues in small-channel devices. To overcome these challenges and design a nanoscale device, an alternate material was needed. Graphene, a novel material with exceptional properties, has been utilized to create a graphene field-effect transistor (GFET) optimized using silicon-on-insulator (SOI) technology. The SOI structure uses graphene as a channel, resulting in the development of a new silicon-on-insulator graphene field effect transistor (SIGFET) with an 18 nm channel length. The designed SIGFET exhibits significant improvements compared to traditional GFET and MOSFET. Specifically, the subthreshold slope (SS) of the SIGFET is 60.93 mV/decade, the drain-induced barrier lowering (DIBL) is 42.89 mV/V, and the ION/IOFF ratio is 6.55×108, which surpasses previous GFET-based contributions and SOI-MOSFET. Moreover, the effect of temperature change on SIGFET performance has been investigated, revealing that temperature variation only affects the drain current and has no impact on short channel characteristics. Therefore, the SIGFET can be an ideal substitute for traditional silicon channel devices.