DESIGN AND OPTIMIZATION OF NUMERICAL METHODS FOR SOLVING PARTIAL DIFFERENTIAL EQUATIONS

High-precision numerical iterations that are memory and computationally demanding are needed to solve partial differential equations (PDEs). In this study, we suggest using the multigrid approach with a hybrid layer update to cut down on iterations and speed up calculation. Additionally, we add a method for converting both fine and coarse grids into a residual form, which significantly lowers the need for precision. Due to the decrease in precision, it is possible to deploy a highprecision PDE solver on low-precision parallel multiply-accumulate (MAC) units contained within SRAMs, which significantly reduces chip size and energy usage. We use a delay-locked loop to generate precisely timed unit pulses that drive the word lines, allowing for more effective operation. In addition, the output from the bitlines is converted using a dual-ramp single-slope analog-to-digital converter (ADC). Four 320 64 MAC SRAMs make up the prototype of our suggested design, which is implemented on a 1.87 mm2 180 nm test chip. Each MAC SRAM has 32 5-bit output ADCs and supports 128 parallel 5-bit MAC operations. The test chip's overall power use when running at 200 MHz is measured at 16.6 mW. The test chip shows through experimental assessment that it is capable of solving PDEs with an error tolerance of 108, while running at a grid update rate of 1.38-G entries per second. The findings demonstrate how well our suggested strategy works in lowering computational iterations, enhancing computational speed, and enabling low-precision parallel MAC operations, opening the door for energy- and space-efficient PDE solving methods