SOFTWARE IMPLEMENTATION OF IC TOPOLOGY TRANSFORMATIONS FOR PROTECTION AGAINST HARDWARE TROJANS

This article focuses on software methods for detecting and preventing the introduction of hardware trojans into the topology of integrated circuits at the design stage. An additional recommendation for typical procedures of receiving GDSII files that significantly complicates the introduction of HTs into the topology is to facilitate detection methods by including special self-test structures created after performing transformations of the initial topology and ensuring the effective examination of ICs at the post-manufacture test stage. The proposed method is based on the analysis of synthesis results at the level of netlist description, its subsequent software conversion into a topological drawing, shifting standard cells and filling created voids with special self-test cells. The method is simple to implement during the topology design stage and can be recommended for use in design centres for machine learning of computer-aided design systems.