FPGA IMPLEMENTATION AND DESIGN OF LOW POWER SEQUENTIAL FILTERJournal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.4, No. 4)
Publication Date: 2015-04-30
Authors : Shivam Singh Sikarwar; Deepak Sharma; Vijay Kumar Sharma;
Page : 504-510
Keywords : FIR filter; Implementation of FIR filter; Micro programmed controller;
We will presents the design and FPGA implementation of sequential digital 8-tap FIR filter using a novel micro programmed controller based design approach. In the paper, the FIR filter is designed for operation controls by micro programmed controller. The proposed FIR filter will be coded in VHDL using modular design approach, and implement in Spartan-3E FPGA. The performance evaluation and synthesis results obtained through Xilinx ISE synthesis tool and functionally checked in Model sim module.
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Last modified: 2015-05-07 19:56:20