Implementation of 8x8 Vedic Multiplier using Verilog

A Multiplier is one of the key hardware blocks in most fast processing system which requires less power dissipation. A conventional multiplier consumes more power. This paper presents a low power 8 bit Vedic. Multiplier VM based on Vertically and Crosswise method of Vedic mathematics a general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. The implementation is done using cadence Virtuoso tool. The power dissipation of 8x8 bit Vedic multiplier obtained after synthesis is compared with conventional multipliers such as Wallace tree and array multipliers and found that the proposed Vedic multiplier circuit seems to have better performance in terms of power dissipation. The essential persistence of this project is to advance the swiftness of the digital circuits like multiplier, meanwhile the multiplier and adder stay unique of the crucial hardware modules in an extraordinary performance systems like DSP digital signal processors , microprocessors and FIR filters etc. Vedic multiplier is alone such extraordinary and swift multiplier architecture. This Vedic Mathematics is the forename specified to the original system of mathematics. It has a sole process of calculations founded on 16 Sutras. The multiplication sutra midst these 16 sutras is the Urdhva Tiryakbhyam sutra which means upright and diagonal. The projected system is designed using Verilog and it is fulfilled over Xilinx ISE 14.2. Mr. Parasurama | Singamsetti Raviteja | Mohamad Shajahan "Implementation of 8x8 Vedic Multiplier using Verilog" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-8 | Issue-2 , April 2024, URL: https://www.ijtsrd.com/papers/ijtsrd64769.pdf Paper Url: https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/64769/implementation-of-8x8-vedic-multiplier-using-verilog/mr-parasurama