DESIGN AND PERFORMANCE ANALYSIS OF TERNARY LOGIC BASED ALU USING DOUBLE PRECISION FLOATING POINT

In digital circuits, particularly space signal applications, the detection/estimation of phase (angle) like milli degree is challenging and involves many complex operations. To estimate milli degree (10-3) or more, floating point operations (like double precision adders, subtractions, multiplications, and divisions) are the significant components and power and area consumption; delays are more in existing works. Existing works mainly concentrate on clock-based synchronous operations, which require more hold, and clock distribution is another major problem due to extra circuitry requirements. The proposed pipelined and clock-efficient distribution system (CEDS) is incorporated in the Floating-Point Unit (FPU) design to address these issues. It includes a double-precision adder, multiplication, division, and subtraction. These FPU and CEDS can be used to detect Milli Degree for GHz frequency in Space applications more accurately. The floating points are essential in phase shift operation used in the space-borne system for effective correction of error checking rather than execution of error analysis in the real-time scenario. Modern digital circuits can hardly improve due to limitations of physical area consumption. The substitution for these limitations, the new digital ternary logic (0, 1, 2), is the solution because of its higher number of digital circuits involved in floating points. The ternary logic is the best solution for the minimization of number bits to optimize memory utilization, and ternary logic has Negative Ternary Inverter (NTI), Ternary Decrement Cycling Inverter (DCI), Standard Ternary Inverter (STI,) and Positive Ternary Inverter (PTI). The proposed design is successfully designed and validated on Zybo Z7-10 (XC7Z010-1CLG400C) FPGA development board. The results show a 45% reduction in power consumption, delay, and area utilization.