AREA AND POWER EFFICIENT LEAST MEAN SQUARE ADAPTIVE FILTER USING APPROXIMATE ARITHMETIC

The efficiency of a digital signal processing system heavily relies on the performance of multipliers, which are crucial arithmetic functional units. Approximate arithmetic techniques have emerged as a promising approach to significantly reduce circuit complexity, latency, and energy consumption. This paper presents a rounding-based approximate multiplier, grounded in approximate arithmetic principles, to execute a Least Mean Square (LMS) adaptive filter. Within the LMS adaptive filter, conventional multipliers are replaced with approximate arithmetic-based multipliers. These approximations simplify the multiplication operations, resulting in reduced area and power consumption. The LMS adaptive filter adjusts filter coefficients based on the LMS algorithm. This proposed system is realized using the Verilog hardware description language, and its performance is validated through simulation and synthesis using Xilinx ISE 14.7 simulator and Vivado design suite. Simulation results showed that implementing the LMS adaptive filter algorithm with rounding-based approximate multipliers yields a substantial reduction in area, latency, and power consumption.