PERFORMANCE EVALUATION OF EFFICIENT STRUCTURE FOR FIR DECIMATION FILTERS USING POLYPHASE DECOMPOSITION TECHNIQUE
Journal: International Journal of Electronics and Communication Engineering and Technology (IJECET) (Vol.6, No. 5)Publication Date: 2015-06-17
Authors : Gopal S. Gawande; Bhavna R. Pawar; K. B. Khanchandani;
Page : 1-8
Keywords : Decimators; Efficient Polyphase Structure; logic area; Polyphase Decomposition; Power consumption; Speed;
Abstract
Multirate signal processing is an enabling technology that brings DSP techniques to theapplications requiring low-cost and high sample rates. Multirate filtering technique is widely used for meeting the sampling rates of different systems. This paper provides implementation and performance comparison ofvarious structures for Decimators usingPolyphase decomposition technique.Polyphase decomposition technique reduces the computational complexity and adopts parallelism. The digital FIR decimator is designed using Filter Design and Analysis (FDA) tool.The structures are synthesized for Spartan6 Field Programmable Gate Array (FPGA) board using Xilinx System Generator. The performance indices for comparing implemented structures using FPGA platform are also proposed in this paper. The proposed efficient polyphase structure consumes 249mWpowers and operates at 121 MHz speed. The efficient structure also yields higher throughput and computation rate compare to other structures used for decimation.The efficient structure shows promising results over the other decimators.
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Last modified: 2015-06-17 16:35:51