A SURVEY ON DESIGN AN EFFICIENT A RCHITECTURE FOR HIGH SPEED CONVOLUTION AND DECONVOLUTION PROCES S

In Digital Signal Processing, the convolution and deconvolution with a very long sequence is ubiquitous in many applicatio n areas. They consume much of time. This paper presents a direct method of computing the discrete linear convolution, circular con volution and deconvolution. The most significant aspect, is the development of a multiplier and divider architecture based on high speed algorithm. It shows that the implementation of linear convolution and circular convolution is efficient in term s of area and speed compared to their implementation using conventional multiplier & divider architectures. In this paper we study different forms of high speed convolution and deconvolution system using FPGA .