A REVIEW ON ADVANCED ENCRYPTION STANDARD (AES) ALGORITHM ON FPGA
Journal: International Journal OF Engineering Sciences & Management Research (Vol.2, No. 5)Publication Date: 2015-05-30
Authors : Ku Sankalpa N. Mohari r;
Page : 26-29
Keywords : FPGA; VHDL; Encryption; Decryption; Cryptography.;
Abstract
A high speed security algorithm is always necessary and important for wired/wireless communication. The symmetric block cipher plays a major role in the bul k data encryption. One of the best existing symmetric security algorithms to provide data security is advanced encryption standard (AES). AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has lot o f advantage such has increased throughput and better security level. Hardware Implementation for generalized AES (Advanced Encryption Standard) encryption and Decryption has been made using VHDL
Other Latest Articles
- A REVIEW OF DESIGN AND SIMULATION OF PARALLEL CRC GENERATION ARCHITECTURE FOR HIGH SPEED APPLICATION
- HIGH SPEED SYSTEM USING VEDIC MATHEMATICS - A SURVEY
- HAND TALK GLOVES FOR GESTURE RECOGNIZING
- SPEECH SIGNAL ENHANC EMENT IN HEAVY NOISE INDUSTRIES
- LITERATURE SURVEY ON VARIOUS CLUSTERING TECHNIQUES USING VIDEO DATA IMAGE
Last modified: 2015-06-23 23:16:38