HARDWARE DESIGN SPACE EXPLORATION OF CORDIC ALGORITHM FOR RUN-TIME RECONFIGURABLE PLATFORM

This paper presents a hardware design space exploration of CORDIC algorithm for implementation on run-time reconfigurable platform. It provides the flexibility to change the performance of current CORDIC implementation in FPGA (Field-Programmable Gate Array) at run time. The performance trade-offs including accuracy, latency, throughput and required logic resources to implement CORDIC algorithm are analyzed. The most optimum design that meets the performance measure is loaded into the reconfigurable platform. The design exploration of CORDIC algorithm is to compute sine and cosine functions including the iterative and the pipelined architectures. The finding shows that the accuracy of computed result increases with the number of iterations but comes with the cost of computation time. The pipelined architecture offers very high throughput compared to iterative architecture with the cost of increased required logic elements. Lastly, this work analyzes the performance trade-off for both iterative and pipelined architectures so that the performance of CORDIC algorithm can be altered at run time when loaded into run-time reconfigurable platform.