Generation of Graph for APB via SPI Verification Using Trek

In VLSI Technologies, according to Moore’s law the density of a semiconducting material increases rapidly. The verification technology in this industry is complex. For verification process, manually generating test cases is difficulty and time consuming process for verifying complex problem in design. For reducing complexity of the verification process is to generate a graph scenario model for each Intellectual Property (IP) blocks in system on chip (SOC) design. The main objective is to verify the IP block of AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) via SPI (Serial Peripheral Interface) using graph based scenario model. This concept includes generation of graph of APB_WB (Advanced Peripheral Bus Wishbone) and integration of test cases generated by the graph to APB. The graph is generated by the software called trek by Breker verification systems. This software automatically generates test cases. These test cases are self-verifying. Trek takes input information from scenario models describing the desired outcomes, developed by the user which is integrated with DUT (Device Under Test) and outcome is verified by Trek mailbox. For more accuracy of SPI protocol, the test cases has to be generated for transmit register using trek.