DIGITAL FM MODULATOR AND DEMODULATOR FOR SDR

This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined Radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features. The modulator and demodulator contain An optimized direct digital frequency synthesizer (DDFS) based on quarter-wave symmetry technique for generating the carrier Frequency with spurious free dynamic range (SFDR) of more than 64 DB. The FM modulator uses pipelined version of the DDFS to Support the up conversion in the digital domain. The proposed FM modulator and demodulator can operate at a maximum frequency of 334.5MHz and 131MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100MHz using Xpower the power has been calculated. The FM modulator consumes 107.67mW power while FM demodulator consumes 108.67mW power for the same input running at same data rate.