DESIGN OF HYBRID QUATERNARY SIGNED DIGIT (QSD) BASED DIVIDER USING VHDL

Arithmetic operations in digital signal processing plays an important. While these operations suffer from many problems like propagation time delay, high power consumption and circuit complexity. QSD number system allows a fast addition, subtraction and m ultiplication. In this paper, we proposed a divider which is made by using QSD technique for fast division without carry propagating delay. In this division method the carry propagation chain are eliminated and reduces the propagation time delay. QSD numbe r system based on quaternary system can be represented by a number from - 3 to 3. The proposed design is developed using VHDL and implemented on Xilinx and results are showed on the ModelSim. The results are compared with the other dividers.