OPTIMIZATION OF AREA IN DIGIT SERIAL MULTIPLE CONSTANT MULTIPLICATION AT GATE LEVEL

ABSTRACT In the last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel multiple constant multiplications (MCM) operation which increases the complexity of many digital signal processing systems. Multiple constant multiplication(MCM) is an efficient way of implementing several constant multiplications with the same input data. The coefficients are expressed using shifts, adders, and subtracters. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low complexity MCM operations. In this paper, we address the problem of optimizing the gate-level area in digit-serial MCM designs.