IMPLEMENTATION OF ADDRESS GENERATOR FOR WiMAX DEINTERLEAVER ON FPGA

In this paper, a low - complexity and novel technique is proposed to implement the address generation circuitry of 2 - D deinterleaver used in the WiMAX transreceiver using the Xilinx field - programmable gate array (FPGA). The floor function is associated with the implementation of the steps,that are required for the permutations of the incoming bit stream in channel interleaver/deinterleaver for IEEE 802.16e standard, it is very difficult to implement in FPGA. In this paper, we develop a simpl e algorithm along with its mathematical background and eliminates the requirement of floor function and allows low - complexity FPGA implementation. The use of the internal multiplier of FPGA and the sharing of resources for 16 - quadrature - amplitude modulati on (QAM),64 - QAM and quadrature phase - shift keying modulations along with all possible code rates makes our approach to be novel and efficient when compared with conventional look - up table - based approach. The proposed approach yields significant improvement in the use of FPGA resources.