AN EFFICIENT REVERSE CONVERTER DESIGN VIA PARALLEL PREFIX ADDER

In this paper, the implementation of residue number system reverse converters based on hybrid parallel prefix adders is analyzed. The parallel prefix adder provides high speed and reduced delay arithmetic operations but it is not widely used since it su ffers from high power consumption. Hence, a hybrid parallel prefix adder component is presented to perform fast modulo addition in Residue Number System reverse conversion. The proposed components are not only results in fast arithmetic operation and it al so highly reduced the hardware complexity since it requires fewer amount of logic elements. In this work, the proposed components are implemented in different moduli sets reverse converter designs and the performances are compared for different values of n .