REDUCING POWER DISSIPATION IN SELF STARTING AND SELF CORRECTING COUNTER USING A LOOK - AHEAD CLOCK GATINGJournal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.4, No. 10)
Publication Date: 2015-10-30
Authors : S.Madhana Mohan; C. Ravi Shankar Reddy;
Page : 306-316
Keywords : starting and Self;
In this paper, a novel Self - starting and Self - correcting counter implemented with some techniques are presented to reduce the power consumption in sequential circuits. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the dynamic power have been developed, of which Data driven method, Auto Gated flip - flop and LACG are predominant. In General way design of Self - starting and Self - correcting counter, it has unfortunately leaves the majority of the clock pulses driving the fli p - flops redundant. Data - driven gating aims to disable these and yields higher power saving, but its depends on which FFs should be placed in a group to maximize power reduction. We propose a practical solution based on the toggling activity correlations of FFs and their physical position proximity constraints in the layout and application dependent. The Power consumption of Auto Gated flip - flop is significantly lower than that conventional flip - flops. By using Auto Gated flip - flop, we can replace convention al FFs in Self - starting and Self - correcting counter to achieve reduction of power dissipation. A third method called Look - Ahead Clock Gating (LACG), which combines above two techniques. LACG computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. It avoids the tight timing constraints of AGFF and data - driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. Simulation results sh ows that the SSSC counter with the Look - Ahead Clock Gating technique reducing power dissipation on an average of 65.44% compared to the conventional SSSC counter and data - driven clock gating SSSC counter.
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