COMPARATIVE ANALYSIS OF 64-BIT DIFFERENT SRAM CELL USING 180NM TECHNOLOGYJournal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.4, No. 11)
Publication Date: 2015-11-30
Authors : Bhawna; Ramanjit Singh;
Page : 257-262
Keywords : CMOS Logic; Low power; Speed; SRAM and VLSI.;
With ever raising demands of battery operated portable device in market is encouraging the VLSI makers to reduce the power dissipation of the electronics devices so that battery backup can be increased. Static Random Access Memory (Static RAM or SRAM) typically occupies the largest portion of the total digital circuit. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and highperformance VLSI circuits. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. Due to the fast improvement for low voltage and low power memory design throughout recent year, SRAM has become the issue of significant research to increase require for laptops, integrated circuit (IC) memory cards, notebooks and hand held communication devices. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choose appropriate techniques that satisfy application and product needs. SRAM have a wide range of applications, due to its many outstanding attributes including huge storage density, small access time and high noise protection. The power consumption and speed of SRAMs are most important topic that provides a solution which describes various designs that minimize the consumption of power. This article is based on the motivation of reduction of the average power consumed in SRAM memory and focuses on the analysis in terms of power dissipation, delay and power delay product of the 6-transistors, 7- Transistors and 8- Transistors SRAM memory cell at 180nm technologies by using the Tanner tool which is having a supply voltage of 1.8 volts. The circuit verification is done on the Tanner tool, Schematic of the SRAM cell is designed on the S- Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit.
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Last modified: 2015-11-17 12:27:13