AREA OPTIMIZED ARITHMETIC AND LOGIC UNIT USING LOW POWER 1-BIT FULL ADDERJournal: International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) (Vol.3, No. 3)
Publication Date: 2013-08-31
Authors : G. KANAKA DURGA; K. SOWJANYA;
Page : 115-120
Keywords : 8 Transistor Full Adder;
In this paper, we proposed a low power 1-bit full adder (FA) with 8-transistors and this is used in the design ALU. By using low power 1-bit full adder in the implementation of ALU, the power and area are greatly reduced to more than 70% compared to conventional design and 30% compared to transmission gates. This design does not compromise for the speed as the delay of the full adder is minimized thus the overall delay. The leakage power of the design is also reduced by designing the full adder with less number of power supply to ground connections. In fact, power considerations have been the ultimate design criteria in special portable applications. For large number of computations, efficient ALU is to be designed for minimum area and speed.
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Last modified: 2013-08-12 13:53:24