Development of 8-lane PCI-Express protocol using VHDL

Flosolver Mk 8 is the latest family member of the Flosolver series of parallel computers in CSIR-NAL that is currently being developed, to have a performance of 10 TFLOPS with 1024 processors in it. It is based on distributed memory concept, using quad core xeon processors[11]. Each cluster consists of 8 processors, a FPGA based Floswitch, and 4 PCI cards. The inter Cluster communication is carried out through optical transceivers to provide high speed communication. PCI is used for interface between the server and the FloSwitch. Unlike any other switch, the Floswitch has the capability of performing information processing operation which is a unique feature, along with message passing[12]. To this existing system the project intends to replace the PCI card with 8-lane PCI-Express add-on card. The PCI-Express defines a line rate of 2.5Gbps per lane. The basic goal of this project entitled “Development of PCI-Express protocol using VHDL” is to Design and Develop a PCI-Express protocol for a 8x PCI-e card, with an optical transceiver and DPM (Dual Port Memory) as an external interfaces. The development includes the generation of 8 x PCI-e cores and interfacing the core for optical transaction and also for the DPM transaction. The PCI-Express add-on card contains a FPGA (Virtex V? XC5VLX110T) and the card supports 8X lane. FPGA provides an interface between the PCI-Express signals, the DPM and the optical transceiver module. The protocol has to be developed using VHDL and simulated using model sim 6.1f.