A LOW POWER SRAM USA GE IN FPGA MEMORY CE LL

Low power has emerged as a principal theme in today’s electronics industry. With ever increasing level of device integration and the growth in complexity of electronic circuits, increasing the demand of portable electronics devices and also depend ence on the battery operated devices motivating the VLSI designers to reduce the power dissipation, of the VLSI circuits. The reduction of power is the most often used measures of the efficiency of VLSI circuits. Low power circuits have long battery life. Power consumption due to memory accesses in a computing system often constitutes the dominant portion of the total power consumption. Measures have to be taken to reduce power consumption in memories. FPGA provide a short time to market and low design cost , which make them increasingly attractive. So a FPGA is designed with various blocks in it.The basic motive of this paper is to analyze the SRAM memory cell which will consume lesser power. FPGA consists of memory block, logical block, switch block, connec tion block. The memory block consists of memory cell. The memory cell used is 10T SRAM cell. The 10T SRAM cell is designed using c2mos logic which consumes less power. The designed 10T SRAM cell is used in the read circuit of the memory block. The logic bl ock and switch block is also designed. Power results of FPGA blocks have been obtained and power results of existing system and proposed system have been compared. Simulation results show significant improvements in reduction of power consumption. All the simulations have been carried out on 180nm technology at Tanner s - edit tool.