HARDWARE CHIP IMPLEMENTATION OF DIGITAL WATERMARKING USING IMDCT INVERSE MODIFIED DISCRETE COSINE TRANSFORM (IMDCT) IN HARDWARE DESCRIPTION LANGUAGE (HDL) ENVIRONMENT

Digital watermarking is the process of embedding data, called a watermark, into a multimedia object such that the watermark can be detected whenever needed for digital rights management (DRM). The object may be an image, audio, video, text, or graphics. In general, any watermarking algorithm consists of three parts: the water mark, the encoder (insertion algorithm), and the decoder and comparator (verification or extraction or detection algorithm). An entity, called the watermark key, which is unique and exhibits a one-to-one correspondence with every water mark, is also used during the process of embedding and detecting the watermark. The key is private and known only to authorized parties, eliminating the possibility of illegal usage of digital content. Different watermarking techniques have already been evolved in the field of digital image processing. Because of copyright protection, watermarking techniques are often evaluated based on their robustness, recoverability, and invisibility. Field programmable gate arrays (FPGAs) are extensively used in rapid prototyping and verification of a conceptual design and also used in electronic systems when the mask-production of a custom IC becomes prohibitively expensive due to the small quantity. In addition to their usefulness as mentioned above, their internal structure also makes them as a suitable vehicle to learn all aspects of VLSI design because they consist of combinational logic in the form of LUT (look up table), flip-flops as sequential building blocks, and memory for programmability. Speed and size are two important factors while designing any system. It’s Speed of operation and flexibility to modify, measures the performance of the system operation. Traffic handling capacity is an important element of service quality and will therefore play a basic role in this choice Microprocessor/microcontroller (MPMC) system can handle sequential operations with high flexibility and use of Field Programmable Gate Array (FPGA) can handle concurrent operations with high speed in small size area. So combined features of both these systems can enhance the performance of the system. Objective is completed in two phases. First phase is designing and second phase is functional simulation and synthesis. Xilinx and Modelsim Simulation tools are proposed to design and verify speed improvement. In our research we considered Inverse Modified Discrete cosine transform (IMDCT) for digital watermarking and its hardware chip implementation with optimized hardware parameters.