Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA
Journal: Mehran University Research Journal of Engineering and Technology (Vol.34, No. 4)Publication Date: 2015-10-01
Authors : Dur-e-Shahwar Kundi; Arshad Aziz;
Page : 441-446
Keywords : Advance Encryption Standard; BRAM; Field Programmable Gate Array; T-Box/T-1-Box;
Abstract
This work presents an efficient implementation of the AES (Advance Encryption Standard) based on Tbox/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption.
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