High Fault Coverage For On Chip Network Using Priority Based Routing AlgorithmJournal: International Journal for Scientific Research and Development | IJSRD (Vol.3, No. 10)
Publication Date: 2016-01-01
Authors : Parul Anand; Chanpreet Kaur Toor;
Page : 930-931
Keywords : Chip network; Bufferless Network;
Network on chip is an interconnection between several processing elements and routers. There are several possibilities for the occurrence of faults within the network. These faults degrade the performance of the network. In order to increase the performance several fault tolerant methods has been used. They involve themselves in rerouting and hence take longer paths. To make the path shorter, the router architecture has to be modified. For this efficient routers are needed to take place communication between these devices. This project, proposes a priority based solution for a bufferless network-on-chip, including an on-line fault-diagnosis mechanism to detect both transient and permanent faults, a hybrid automatic repeat request and forward error correction link-level error control scheme to handle transient faults.
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Last modified: 2016-01-11 17:36:02