ANALYSIS AND REDUCED THE COMPLEXITY OF ADPLL DESIGN ARCHITECTURE WITH K - BEST MIMO DETECTOR UP TO 1.5 GHZ
Journal: International Journal OF Engineering Sciences & Management Research (Vol.3, No. 2)Publication Date: 2016-02-28
Authors : Eswaran.G; Mounika.R;
Page : 10-15
Keywords : MIMO (Multiple Input Multiple Output); QAM - Quadrature Amplitude Modulator; TDC - Time To Digital Converter; ADPLL - All Digital Phase Locked Loop;
Abstract
A 7 ps/LSB, 0.02 mm2 and 3.9 mW@50MHz Time to Digital Converter architecture with novel MIMO detector. Which aims to solve the 4 ×4 64 - QAM in high - speed applications. Multiple ring oscillators with unique and variable frequencies are used in order to make N independent measurement s of the time pulse to be measured M times in order to create transmitter and receiver diversity similar to those in MxN MIMO antenna arrays. We propose a fully - pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the de tection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 nm CMOS technology and has 366K gates.
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Last modified: 2016-01-28 20:08:15