GLITCH - FREE NAND - BASED DIGITALLY CONTROLLED DELAY LINES

Glitch is an undesired transition that occurs before the signal settles to its intended value. It is an electrical pulse of short duration that is usually the result of a fault or design error, particularly in a dig ital circuit. The existing Glitch Free NAND - based Digitally Controlled Delay Lines (DCDL) presented some glitching problem which limited their applications. To overcome this limitation new NAND - based DCDL is proposed. This will maintain the same resolution and minimum delay of existing NAND - based DCDL. The proposed DCDL will be working on the basis of two control signals which are used to avoid glitches. The delay elements are composed of NAND gates. The state of the delay elements is based on the control s ignals. By applying control signals at minimum delay to the NAND gates, the glitches can be avoided. The driving circuits for the delay control bits are proposed.