A DYNAMIC LATCHED COMPARATOR FOR LOW SUPPLY VOLTAGES DOWN TO 0.45 V IN 45-NM CMOS USED IN FLASH ADC

Comparators are known as 1-bit analog-to digital converter and for that reason they are mostly used in large abundance in A/D converter. . In the analog-to-digital conversion process, it is necessary to first sample the input. This sampled signal is then applied to a combination of comparators to determine the digital equivalent of the analog signal. The conversion speed of comparator is limited by the decision making response time of the comparator.A Novel High Speed CMOS Comparator with low power dissipation, low offset, low noise and high speed is proposed and suitable for applications with very low supply voltage. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This comparator is designed in 45-nm CMOS technology with standard threshold transistors (VT?0.4V). Simulation shows that it achieves 5mV sensitivity for a sampling rate of 5.2GS/s with 1.2V supply voltage, 10mV for 250MS/s with 0.5V supply voltage and 100MS/s with 0.45V supply voltage. The simulated delay time of the proposed comparator is about 30% shorter than the dual-tail dynamic comparator with 0.5V supply voltage and only one third compared to that of the conventional one with 0.8V supply voltage when they are designed to have a similar input referred offset voltage in 45nm CMOS technology. The proposed circuit is developed on CADENCE gpdk-45 Spectre simulator