Generalized Parallel CRC Computation

This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from the degree of the polynomial generator. Last, we from which our parallel implementation is derived. In comparison with previous works, the new scheme is faster and more compact and is independent of the technology used in its realization. In our solution, the number of bits processed in parallel can be different have also developed high-level parametric codes that are capable of generating the circuits autonomously when only the polynomial is given.