IMPLEMENTATION OF VLSI ARCHITECTURE FOR RECONFIGURABLE RRC FIR FILTER USING GRAPH BASED METHOD

The essential factors which contributes for designing the architecture of reconfigurable pulse shaping FIR filter are low complexity and power consumption. Although several low complexity architectures have been used for the optimization of Multiple Constant Multiplication (MCM), ie., the multiplication of a data sample by set of constants, further improvement in area and power consumption for RRC FIR filter design can be accomplished by employing the highly efficient algorithms. Hence the Graph Based (GB) algorithm had been implemented in RRC FIR filter. These GB methods are not limited to any particular number representation such as CSD, MSD, Binary and it yields better solutions than shift add implementation of constant multiplication. It is also capable of operating for different wordlength filter coefficients without any expense over the hardware circuitry. Hence it has been observed from the experimental result that the architecture using GB algorithm offers efficient area reduction and power consumption when compared to existing reconfigurable implementations using BCSE algorithm.