AN FPGA REALIZATION OF INTEGRATED EMBEDDED MULTI- PROCESSORS SYSTEM: A HARDWARE- SOFTWARE CO- DESIGN APPROACH

A comprehensive technique for FPGA realization of integrated embedded multi- processors system based on hardware- software co- design approach is presented. In order to demonstrate the proposed technique, a matrix multiplication algorithm has been used. The matrix multiplication algorithm is implemented as a synthesizable streaming- loop MATLAB program from which a System Generator block is obtained using Xilinx AccelDSP. Using the System Generator block, the Xilinx System Generator for DSP is then employed to create a complete hardware model of the matrix multiplication algorithm and subsequently the matrix multiplication algorithmic processor system. Then, an embedded PowerPC™440 processor system is designed and tested using the Xilinx platform studio (XPS) and the Xilinx software development kit (SDK) respectively. Next, the matrix multiplication algorithmic processor is exported to and integrated as a co- processor with the embedded PowerPC™440 processor system within the XPS while the software portion of the embedded system is developed within the SDK. Finally, the embedded multi- processors system is compiled and programmed into a Virtex-5 FX70T ML507 FPGA board. Some experimental results are presented and conclusions are drawn with some discussions on future directions.