Design & Simulation of Dual Elevator
Journal: International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) (Vol.3, No. 4)Publication Date: 2013-10-31
Authors : Kumar. Keshamoni Ajamal Sadiq. Mahammad; Raghavendra K;
Page : 41-48
Keywords : CSM; FSM; Verilog HDL; XILINX; Elevator; FPGA; ASSP; Controller;
Abstract
In modern life, elevators have become an integral part of any public or commercial complex. It does not only ease the faster movement between any two floors and provide a way for movement of disabled, but has also become a status symbol. Elevators, as usually been called as “cars” which work on a gearless traction system in which the movement of the elevator is controlled by several steel hoist ropes and a counter-weight. The weight of the car and counterweight provides sufficient traction between the sheaves and the hoist ropes so that the sheaves can grip the hoist ropes and move and hold the car without excessive slipping. The machinery to drive the elevator is located in a machine room usually directly above the elevator hoist way. Elevator controller controls the entire operation of the Dual elevator system. The proximity sensors located to sense the positions of the cars, provide the current state storing it in register. The obstruction sensors provide the status of obstruction. The elevator controller also reads the requests, if any, from any of the request positions through the flip-flops. If the door of any elevator is open, the timer signals from the elevator keep the controller informed of being busy. The control state machine receives all these signals. It is programmed to the algorithm by which it should control the system. The CSM then generates control signals for the next position and movement of the elevators. Elevators on receiving the signal address to the request, as been asked by the controller. In this work, the real-time Dual elevator controller will be modeled with Verilog HDL code using Finite-State machine (FSM) model to achieve the logic in optimized way.
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Last modified: 2013-09-04 14:25:05